1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same and, more particularly, to a by-pass capacitor disposed between a power source potential node and a ground potential node and a method of manufacturing the same.
2. Related Background Art
In a semiconductor integrated circuit, as a countermeasure against EMI (Electro Magnetic Interference) of canceling off power source noise between a power source potential node and a ground potential node, entering from the external via the power source potential node and the ground potential node, a by-pass capacitor is disposed between the nodes.
The following five modes can be mentioned as conventional modes of disposing a by-pass capacitor between a power source potential node and a ground potential node of a semiconductor integrated circuit.
In a first conventional mode, by using a source potential and a drain potential of an n-channel MOS transistor as a ground potential and using a gate potential as a power source potential, or by using a source potential and a drain potential of a p-channel MOS transistor as a power source potential and using a gate potential as a ground potential, a by-pass capacitor including a gate insulation film made of a dielectric is formed.
In a second conventional mode, a power source potential pad and a ground potential electrode pad are disposed so as to be adjacent to each other and a metal wiring led from one of the electrode pads is laid under the other electrode pad via an interlayer insulation film, thereby forming a by-pass capacitor including an interlayer insulation film made of a dielectric.
In a third conventional mode, a power source potential lead frame and a ground potential lead frame are disposed so as to be adjacent to each other in an LSI package and only the portion between the lead frames is molded by a ferromagnetic, thereby forming a by-pass capacitor using the molding material as a dielectric.
In a fourth conventional mode, a by-pass capacitor is mounted and connected as a separate part near a power source terminal and a ground terminal of an LSI on a mounting board.
In a fifth conventional mode, when a dummy trench exists under an electrode pad in a DRAM embedded LSI or the like, a by-pass capacitor is formed by using the dummy trench. Refer to Japanese Patent Laid-Open Pub. No. 08-274258 (274258/1996) as an example of the fifth conventional mode.
One of various capacitors is an MIM (Metal-Insulator-Metal) structure capacitor. Structures to achieve smaller size and larger capacitance of the MIM structure capacitor have been proposed. As an example of such a structure, refer to Japanese Patent Laid-Open Pub. No. 2001-102529.
Each of the conventional modes has, however, the following problems.
In the first conventional mode, since an area for forming a by-pass capacitor is limited in an LSI in which the ratio of area of transistors used for an internal circuit is high, it is difficult to obtain large capacitance. Moreover, since the gate insulation film is used as a dielectric, the possibility of destruction of the gate insulation film is high.
In the second conventional mode, the interlayer insulation film used as a dielectric is thick, so that it is difficult to obtain a large capacitance. Since wirings of different potentials are laid under electrode pads, short-circuit tends to occur between the power source and the ground by a probe pressure applied at the time of wafer measurement.
In the third conventional mode, a different material is used only for a part of the molding, so that the molding process is complicated and the number of steps also increases.
In the fourth conventional mode, the number of mounting parts increases, so that it causes increase in the failure rate at a mounting level and increase in the mounting area and volume.
In the fifth conventional mode, in the case of a circuit device other than a DRAM embedded LSI, the number of steps for forming a trench capacitor increases and it causes increase in manufacturing time and cost.